GRAYnomad :: backplane

Backplane

The Quub backplane has 48 signals on two 24-way headers, these signals consist of up to 32 general-purpose IO signals from the core processor plus power and debugging signals.

The headers used are typically the stackable type with long tails, however the bottom board in a Quub stack would normally have short solder tails and the top board may only have header pins underneath the board with no matching sockets on the top.

The standard connector is a Samtec SSQ-1-12-23-F-D which is a 12x2 header, if this cannot be sourced then 4 of the Arduino 6-way stackable headers can be used.

Note that the core processor does not have to be at the bottom of the stack, normally it would be but there may be applications where another type of board is a more appropriate choice, say a tiny robot where the bottom board has the motors and motor-driving circuitry.

P1 connector pinout

Descriptions of some signals.

AN-00:07 - These are connected to ADC inputs of the core processor. Any not used for analogue input can be used as general-purpose IO.

DBG-00:03 - Special-purpose debugging signals.

SSDAT - A data output from the core processor used to communicate information to the Stackable Control Chips.

SSCLK - A clock output from the core processor used to communicate information to the Stackable Control Chips.

SSACK - An input to the core processor that indicates that a selected stackable has in fact been selected. This is diode-ANDed with all the BRDEN signals on addressable stackables.

INTREQ - An active low signal used by stackables to request an interrupt of the core processor. Driven low by stackables when requesting the interrupt, high-impedance at other times (pulled high by the core processor's pullup resistor).

INTACK - An output from the core processor that acknowledges the interrupt request on INTREQ.

MOSI - The SPI data output from the core processor and input to all slave processors.

MISO - The SPI data input to the core processor and output from all slave processors.

SCK - The SPI clock signal, driven by the core processor.

IVECT-00:02 - Interrupt vector signals (shared with the SPI signals). These signals hold the vector of the interrupting slave processor shortly after INTACK is driven low.

PGM - This signal is driven low to indicate that the SPI signals are being controlled by a programmer and not the system processors. Used enable flash programming of the stackable's processor.

P2 connector pinout

Descriptions of some signals.

RXD-00 - Serial input to the core processor's hardware UART #0.

TXD-00 - Serial output from the core processor's hardware UART #0.

RXD-01 - Serial input to the core processor's hardware UART #1 (if available).

TXD-01 - Serial output from the core processor's hardware UART #1 (if available).

SCL/SDA - I2C data and clock signals.

DBG-02:03 - Used by the core processor to form a high-speed synchronous link to a debugging tool. If this is the case IO-26:29 are not available to the backplane for general-purpose IO.

CC-00:01 - Connected to comms site #1 and used for general IO to/from the comms site. For example these signals can be used to enable the receiver and transmitter of an RS-485 transceiver chip.

CC-02:03 - Connected to comms site #2 and used for general IO to/from the comms site.

RST - The system reset/brownout signal. Driven by a hardware supervisor chip on the core processor board. Open collector/drain and therefore can also be driven by a stackable.

RPIN-01/01/05/06 - These four signals are connected to the pins 1, 2, 5 and 6 on the rear connector. If the rear connector is not used these can be general-purpose signals to be used as you see fit.

		Backplane
		The Quub backplane has 48 signals on two 24-way headers, these signals consist of up to 32 general-purpose IO signals from the core processor plus power and debugging signals. The headers used are typically the stackable type with long tails, however the bottom board in a Quub stack would normally have short solder tails and the top board may only have header pins underneath the board with no matching sockets on the top. The standard connector is a Samtec SSQ-1-12-23-F-D which is a 12x2 header, if this cannot be sourced then 4 of the Arduino 6-way stackable headers can be used. Note that the core processor does not have to be at the bottom of the stack, normally it would be but there may be applications where another type of board is a more appropriate choice, say a tiny robot where the bottom board has the motors and motor-driving circuitry.
		P1 connector pinout
		Descriptions of some signals. AN-00:07 - These are connected to ADC inputs of the core processor. Any not used for analogue input can be used as general-purpose IO. DBG-00:03 - Special-purpose debugging signals. SSDAT - A data output from the core processor used to communicate information to the Stackable Control Chips. SSCLK - A clock output from the core processor used to communicate information to the Stackable Control Chips. SSACK - An input to the core processor that indicates that a selected stackable has in fact been selected. This is diode-ANDed with all the BRDEN signals on addressable stackables. INTREQ - An active low signal used by stackables to request an interrupt of the core processor. Driven low by stackables when requesting the interrupt, high-impedance at other times (pulled high by the core processor's pullup resistor). INTACK - An output from the core processor that acknowledges the interrupt request on INTREQ. MOSI - The SPI data output from the core processor and input to all slave processors. MISO - The SPI data input to the core processor and output from all slave processors. SCK - The SPI clock signal, driven by the core processor. IVECT-00:02 - Interrupt vector signals (shared with the SPI signals). These signals hold the vector of the interrupting slave processor shortly after INTACK is driven low. PGM - This signal is driven low to indicate that the SPI signals are being controlled by a programmer and not the system processors. Used enable flash programming of the stackable's processor.
		P2 connector pinout
		Descriptions of some signals. RXD-00 - Serial input to the core processor's hardware UART #0. TXD-00 - Serial output from the core processor's hardware UART #0. RXD-01 - Serial input to the core processor's hardware UART #1 (if available). TXD-01 - Serial output from the core processor's hardware UART #1 (if available). SCL/SDA - I2C data and clock signals. DBG-02:03 - Used by the core processor to form a high-speed synchronous link to a debugging tool. If this is the case IO-26:29 are not available to the backplane for general-purpose IO. CC-00:01 - Connected to comms site #1 and used for general IO to/from the comms site. For example these signals can be used to enable the receiver and transmitter of an RS-485 transceiver chip. CC-02:03 - Connected to comms site #2 and used for general IO to/from the comms site. RST - The system reset/brownout signal. Driven by a hardware supervisor chip on the core processor board. Open collector/drain and therefore can also be driven by a stackable. RPIN-01/01/05/06 - These four signals are connected to the pins 1, 2, 5 and 6 on the rear connector. If the rear connector is not used these can be general-purpose signals to be used as you see fit.