GRAYnomad :: core processors

Core processors

Although originally designed with AVR processors in mind the Quub system is largely processor independent, meaning that you can design a core processor board using any modern microcontroller.

Current versions at the design stage are...

MEGA-Quub — Based on an AVR ATmega1284 processor this is currently the most powerful core processor.

DUINO-Quub — This is based on the ATmega328 processor, it is functionally equivalent to the Arduino Duemilanove.

PIC-Quub — Based on the PIC 18F2520, a quite powerful processor with similar capabilities to the ATmega328 used in the Duino-Quub.

PICAXE-Quub — Speed wise this is the baby of the core processors, however it still has access to most of the Quub facilities. It sports a Picaxe 20x2.

These core processors have different capabilities, however they all have the same physical form factor and can all make use of Quub stackables as well as Arduino shields by using an Ardaptor.

Core processor capabilities

As much as possible all Quub core processor boards should support the following features.

Rear comms and power connector — A 6-way header mounted near the centre of the PCB. This is designed to allow access for a cable entering through the rear of the enclosure, thus a device can be bulkhead mounted with no visible wiring. VBAT-RAW and GND are connected to this header as are two uncommitted signals from the comms interface boards. These two connections allow for most common network scenarios such as RS-485 etc. Thus a device can be powered and networked through the rear of the enclosure.

Stackable IO boards — The 24-way headers on each side of the processor board allow for stacking of daughter boards, known as "stackables". There is no practical limit to the number of boards that can be stacked, and in general any board can be in any position. The processor does not have to be at the bottom, so for example a small robot could have a motor/gearbox board underneath the processor.

Addressable IO boards — Up to 9 (expandable to 16) stackables can be "addressable", meaning that the processor can select them one at a time and therefore they can share the processor's IO pins.

The core processor should therefore have the ability to perform this addressing, this requires three pins, two to transmit an address as an sync byte on the SSCLK and SSDAT signals, and another to read an acknowledge level on the SSACK signal.

Multi-processor communications — The Quub system is designed to allow multiple processors to operate concurrently. This feature is not designed to allow multi-tasking in the sense of running a program in separate threads, it allows IO tasks (for example controlling servos, handling distance sensing, reading and filtering IO, or dealing with mass-storage or display devices) to be offloaded by the core processor and provides a mechanism by which slave processors can communicate with the core processor.

To allow high speed (up to 5Mbps) co-processors communicate with the core processor using the three SPI signals, all processors have these signals wired in parallel but only the processor on a selected stackable will respond to commands sent by the core processor.

The core processor must therefore be able to communicate using the SPI protocol.

Another option is to use I2C, the core processor should provide pullup resistors on the backplane SDA and SCL signals to allow I2C communicaions with no extra hardware.

Slave processor interrupts — Co-processors can also interrupt the core processor, a simple hard/software protocol is defined that allows slaves to provide their interrupt priority as a response to an interrupt acknowledge from the core. In the case of simultaneous interrupts the stackable with the highest priority (ie lowest value) will be serviced first.

Communications "sites"
A Quub core processor board should support both comms sites if possible, exactly what is supported is up to the board designer.

		Core processors
		Although originally designed with AVR processors in mind the Quub system is largely processor independent, meaning that you can design a core processor board using any modern microcontroller. Current versions at the design stage are... MEGA-Quub — Based on an AVR ATmega1284 processor this is currently the most powerful core processor. DUINO-Quub — This is based on the ATmega328 processor, it is functionally equivalent to the Arduino Duemilanove. PIC-Quub — Based on the PIC 18F2520, a quite powerful processor with similar capabilities to the ATmega328 used in the Duino-Quub. PICAXE-Quub — Speed wise this is the baby of the core processors, however it still has access to most of the Quub facilities. It sports a Picaxe 20x2. These core processors have different capabilities, however they all have the same physical form factor and can all make use of Quub stackables as well as Arduino shields by using an Ardaptor.
		Core processor capabilities
		As much as possible all Quub core processor boards should support the following features. Rear comms and power connector — A 6-way header mounted near the centre of the PCB. This is designed to allow access for a cable entering through the rear of the enclosure, thus a device can be bulkhead mounted with no visible wiring. VBAT-RAW and GND are connected to this header as are two uncommitted signals from the comms interface boards. These two connections allow for most common network scenarios such as RS-485 etc. Thus a device can be powered and networked through the rear of the enclosure. Stackable IO boards — The 24-way headers on each side of the processor board allow for stacking of daughter boards, known as "stackables". There is no practical limit to the number of boards that can be stacked, and in general any board can be in any position. The processor does not have to be at the bottom, so for example a small robot could have a motor/gearbox board underneath the processor. Addressable IO boards — Up to 9 (expandable to 16) stackables can be "addressable", meaning that the processor can select them one at a time and therefore they can share the processor's IO pins. The core processor should therefore have the ability to perform this addressing, this requires three pins, two to transmit an address as an sync byte on the SSCLK and SSDAT signals, and another to read an acknowledge level on the SSACK signal. Multi-processor communications — The Quub system is designed to allow multiple processors to operate concurrently. This feature is not designed to allow multi-tasking in the sense of running a program in separate threads, it allows IO tasks (for example controlling servos, handling distance sensing, reading and filtering IO, or dealing with mass-storage or display devices) to be offloaded by the core processor and provides a mechanism by which slave processors can communicate with the core processor. To allow high speed (up to 5Mbps) co-processors communicate with the core processor using the three SPI signals, all processors have these signals wired in parallel but only the processor on a selected stackable will respond to commands sent by the core processor. The core processor must therefore be able to communicate using the SPI protocol. Another option is to use I2C, the core processor should provide pullup resistors on the backplane SDA and SCL signals to allow I2C communicaions with no extra hardware. Slave processor interrupts — Co-processors can also interrupt the core processor, a simple hard/software protocol is defined that allows slaves to provide their interrupt priority as a response to an interrupt acknowledge from the core. In the case of simultaneous interrupts the stackable with the highest priority (ie lowest value) will be serviced first. Communications "sites" A Quub core processor board should support both comms sites if possible, exactly what is supported is up to the board designer.