Stackables
		The Quub system allows for up to 9 (expandable to 16) daughter boards to be stacked with the processor board. These daughter boards are known as "stackables". Stackables are normally the same size as the processor boards (1.8x1.8") however they can be larger if required. A range of stackables are currently being designed. MEGIO - This is an intelligent IO board capable of driving up to 45 hardware IO channels with no intervention from the core processor. 4DIF - An interface to several 4D-systems LCD/OLED displays (some with touch panel) and also to their microSD card module. This stackable also has a real time clock with battery backup. Depending on the module connected 2GB of data can be stored on the SD card. The RTC can be set to wake the entire Quub stack using the alarm feature. HMI-LED - A simple human-machine interface, features a single 3-digit 7-segment LED display and five tactile pushbutton switches. This stackable also has a peizo buzzer that can be used as an alarm and it can control the power supply to itself and/or the entire Quub stack. All these stackables are addressable, so any combination can be used at the same time, for example you could have a system with 9 stackables to give access to 100s of inputs and/or outputs on a single Quub system. Then of course you can network Quubs for more IO or use stackables that handle more IO. Smart stackables can often also be used as stand-alone processors and as Arduino clones, this allows them to be used for applications such as simple meters and data loggers without the full Quub stack overhead.
		Stackable "backplane"
		The "backplane" used to connect stackables is made up of two 24-way stackable connectors. These connectors (P1 and P2) carry all 32 of the core processor's IO lines plus DBG00-03, RST, PGM, VBAT-RAW, VBAT-SYS, VCC, V3V3, AREF and 2 user-definable signals Any number of stackables can be stacked and they can be mounted above and/or below the processor board (subject to the type of connectors loaded). See the backplane page for more information.
		Addressing modes
		There are two methods of addressing stackables, either no addressing at all or being addressed as one of up to 9. This obviously allows a vast increase in the IO that can be connected, however the main reason for this feature is to allow... Boards from different manufacturers to be connected without worrying about whether or not they use the same pins. Identical boards to be mounted. Obviously without an addressing feature identical boards are guaranteed to clash as they use the same pins. Dumb logic. Not addressable, just 32 IO lines read directly by the processor. In this mode all 32 IO signals are available to a stackable. Multiple stackables can be mounted but normal signal-clashing issues apply so if all 32 IO signals are used by a board no others can be mounted on the stack. Stackables using this mode can co-exist with smart stackables as long as the dumb board doesn't use the IO-00:07 backplane signals. In this case only 24 IO signals are available to the dumb stackable. Under some circumstances fewer IO signals may be available, it depends on the configuration of the core processor and other stackables. Dumb logic. Addressable using SCC (Stackable Control Chip), number of IO lines used depends on the design but all must be tri-stateable so boards can share signals.   Stackables using this mode can co-exist with smart stackables as long as the dumb board doesn't use the IO-00:07 backplane signals. In this case only 24 IO signals are available to the dumb stackable. Under some circumstances fewer IO signals may be available, it depends on the configuration of the core processor and other stackables. IO expander chips can use the SPI interface the same as a smart stackable, in this case 24 IO signals are available. Addressable with co processor. This mode uses up to 8 backplane signals. Up to 9 smart stackables can be mounted and the remaining 24 backplane signals still are available for use by dumb stackables.   If a co processor does not use interrupts only 5 backplane signals are used, 2 for the SCC chip and 3 for the system, SPI. Another 3 signals are used if the co processor does use interrupts.
		Stackable addressing
		Smart or dumb stackables can also be addressed by the processor using "smart addressing'. The processor uses a simple algorithm to address stackables and the stackable board has to have a decoder chip installed. The algorithm can accommodate any number of stackables, however a limit of 9 has been set with provision for expansion to 16. This feature uses three of the available IO signals. Stackables do not have to be addressable to work in the system and both addressable and non-addressable boards can coexist as long as the IO signals they use don't clash. Stackables can be dumb IO boards or intelligent co-processors. How does it work? To be addressable a stackable must have a decoder chip installed, this is a custom chip (a pre-programmed ATtiny85) known as the Stackable Control Chip or SCC. NOTE: Technically an intelligent stackable doesn't need the SCC as it can perform the same functions on its own behalf. However such an arrangement is an invitation for trouble as a crashed or otherwise faulty application program could disable the entire system, or the application may just not be fast enough to respond. The SCC runs a tightly-written assembly routine that is little more than the equivalent of a few logic gates and a shift register, it can be treated as hardware and should be as reliable. The SCC program will be available under a Creative Commons BY-SA license, the source code and HEX files will be available for downloading. If you can't program AVRs then the pre-programmed chips will be available at cost price. The SCC pins functions are as follows. SSCLK - The clock for a synchronous data link used by the core processor to control the SCC. SSDAT - The data for a synchronous data link used by the core processor to control the SCC. A0/1 - Used to set the stackable address. These pins are trinary encoded therefore 9 addresses can be set, they are read at reset to determine the stackable address then turned to outputs to provide the BRDEN and DBGEN signals. BRDEN - Active low when the stackable is selected, this is diode-ORd on the backplane with all other stackables to become the SSACK backplane signal. DBGEN - Active high when the stackable is granted access to the debug bus. If the board doesn't use the debugging facilities this pin can be used as a general-purpose control line. BRDCNTL - A general-purpose control signal; on an intelligent stackable this signal is used to reset the processor. If not used for this function it can be used as a general-purpose control line. Trinary encoding Because the A0 and A1 pins are connected internally to ADCs on the SCC we can determine voltage levels aside from the usual 0 and 5v readable on a digital pin. Therefore only two pins are needed to encode 9 addresses. Address A0 A1 0 0v 0v 1 3v3 0v 2 5v 0v 3 0v 3v3 4 3v3 3v3 5 5v 3v3 6 0v 5v 7 3v3 5v 8 5v 5v NOTE: Trinary encoding is used to save pins and PCB space on the stackable board, however the control byte allows for up to 16 addresses so expansion of the system is possible with a different SCC design. Control byte The core processor sends a control byte to all SCCs, this has the following format. The lower 4 bits of the control byte are the address, of which only 9 addresses are used by the current SCC design. If the SCC determines that the control byte is intended for it the next three bits will be written directly to the BRDEN, DBGEN and BRDCNTL pins. Operation The core processor sends a byte in the above format to all SCCs at the same time. Every SCC will be interrupted by the first bit and will deselect its board by raising BRDEN. Thus at some point during the transmission of the control byte SSACK will go high. When the entire byte is received the addressed SCC will lower BRDEN and by extension also SSACK. The entire context switch then occurs in 8 cycles of the SSCLK signal. What happens on the stackable board? In a nutshell a deselected stackable must ensure that all signals it outputs to the backplane are tri-stated and input signals ignored. On a intelligent stackable with a processor this would normally mean disabling the SPI pins , this is most easily done by routing the BRDEN signal to the co-processor's SS pin. If the board uses an IO expander chip it will also have an SS (or CS) pin that will serve the same purpose. On a dumb board tri-state buffers will be disabled.
		Stackable interrupts
		Smart stackables can interrupt the core processor. A simple algorithm is defined to allow the core processor to set priority levels. Up to 15 priority levels can be assigned, however with the current SCC design only 9 stackables can be addressed and therefore be enabled to interrupt the core processor. Interrupting may or may not be faster than polling, it depends on the number of stackables and all sorts of system requirements, however there are many situations where interrupting makes sense, for example. Real time clock - An RTC on a stackable can be set to interrupt every minute, hour, day or whatever. Thus the core processor doesn't have to constantly poll the RTC, in fact the entire system can lay dormant until the interrupt occurs. Intelligent IO - A stackable with a slave processor can be set to monitor any number of IO conditions and only interrupt the core processor when a change has occurred and then only if the change has exceeded a pre-determined amount. Thus 100s of IO events can be monitored with almost no load on the core processor. Automated control - A stackable that for example monitors a temperature and controls a fan to limit the temperature can do this autonomously with no input from the core processor. However if an error is detected, say the temperature keeps rising regardless of the fan, the alarm can be raised to the core processor. Mechatronics - A stackable can be designed to operate say 8 servos, once told the position of each servo it carries on independent of the core processor but will interrupt if an error condition occurs, such as excessive current draw indicating that something is obstructing a servo mechanism. Robotics - A stackable with ultra-sonic range sensors, accelerometers, and tilt sensors can be designed to monitor the robot's environment and attitude, only interrupting the core processor when an object is too close, the chassis is in danger of tipping over or has collided with something. Data logging - A data logging stackable can log data until it's local memory is nearly full at which point it interrupts the core processor and offloads to a mass storage stackable. Thus the writes to mass storage are only performed in 4k blocks not every time something changes state.   How does it work? A slave processor interrupts the core by lowering the INTREQ backplane signal, and waiting for INTACK to also go low indicating that the core processor is ready to service the interrupt. The slave then places its priority level (allocated previously by the core processor) onto the three SPI signals MOSI (IVECT-00), MISO (IVECT-01) and SCK (IVECT-02) with the proviso that only those priority bits that are low are driven, any high bits are left as inputs and are therefore at a high-impedance state. This allows multiple slaves to interrupt at the same time, with the priority having the lowest number winning because any 0 bit will override a 1 bit. Having acknowledged the interrupt the core processor monitors the IVECT signals waiting for them to change from the default value of 7 (all high) to any other value. When they do it reads the value from the IVECT signals then raises INTACK and waits for the IVECT signals to return to their default value, indicating that the slave has "acknowledged the acknowledge" by sending all it's IVECT signals to a high-impedance state. The IVECT value is then used to select the interrupting stackable and a poll is performed to get whatever data was considered so important. Because the default (un driven) state for the three IVECT lines is high the value 7 is read from them when no slave is driving the signals, therefore vector 7 cannot be allocated as an interrupt priority because it is not discernable from the default state. Therefore although 9 smart stackables can be addressed, only 8 of them can be enabled to interrupt the core processor.
		Stand-alone stackables
		Smart stackables have an on-board microcontroller, they can often therefore be used as stand-alone devices. The Quub backplane groups certain signals to accommodate this. Current designs use an ATmege8 as the processor, however this is pin-compatible with the ATmega168 and 328 so an application that requires more memory can use the same stackable with a more powerful processor.